1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal panel having a step-compensating pattern and a fabricating method thereof.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device makes use of optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientational alignment that results from their thin, long shape. The alignment direction of the liquid crystal molecules can be controlled by application of an electric field to the liquid crystal molecules. Accordingly, as an intensity of the applied electric field changes, the alignment orientation of the liquid crystal molecules also changes. Since incident light through a liquid crystal material is refracted due to an orientation of the liquid crystal molecules resulting from the optical anisotropy of the aligned liquid crystal molecules, an intensity of the incident light can be controlled and images can be displayed.
Among the various type of LCD devices commonly used, active matrix LCD (AM-LCD) devices where thin film transistors (TFTs) and pixel electrodes connected to the TFTs are disposed in matrix have been developed because of their high resolution and superior display of moving images.
FIG. 1 is a plan view of a liquid crystal panel for a liquid crystal display device according to a related art. In FIG. 1, a liquid crystal panel includes an active region “I” and a non-active region “II” disposed at a peripheral portion of the active region “I.” First and second substrates 10 and 30 face each other, and a seal pattern 40 for attaching the first and second substrates 10 and 30 is formed between the first and second substrates 10 and 30. A liquid crystal material layer 50 is disposed at an interior region of the seal pattern 40, and is formed by injecting liquid crystal material through an injection hole 42 of the seal pattern 40. After injecting the liquid crystal material, the injection hole 42 is closed with a bonding seal 44 to prevent a leakage of the injected liquid crystal material.
A plurality of gate lines 12 and a plurality of data lines 14 are formed at the active region “I,” to cross each other, a thin film transistor (TFT) “T” is disposed at a cross of the gate line 12 and the data line 14, and a pixel electrode 16 is connected to the TFT “T.” Although not shown in FIG. 1, a color filter layer, which includes red, green, and blue sub color filters, a black matrix, which is formed at a borderline between the adjacent sub color filters and a non-pixel region, and a common electrode are all formed on an interior surface of the second substrate 30.
The non-active region “II” is classified into a first non-active region “IIa” and a second non-active region “IIb,” wherein the first non-active region “IIa” is disposed on the first substrate 10 and the second non-active region “IIb” is disposed on the second substrate 30 to be surrounded by the first non-active region “IIa.” A gate pad 18 that connects the gate line 12 and an external circuit, and a data pad 20 that connects the data line 14 and an external circuit are formed within the first non-active region “IIa.”
Array patterns, such as the gate line 12 and the data line 14, are formed through a photolithographic process where the same photoresist (PR) patterns as the array patterns are obtained by selectively exposing the PR of a photosensitive material using a photo mask. Chemical and physical process steps are repeated during the photolithographic process. As the number of the process steps increases, fabrication costs and possibilities of damage to the array patterns also increase. Accordingly, a fabricating process using a reduced number of masks has been developed. Thus, a five mask process that includes steps of forming a gate line, a semiconductor layer, a data line, a contact hole, and a pixel electrode may be replaced with a four mask process where the steps of forming the semiconductor layer and the data line are combined into a single step.
FIGS. 2A to 2C are cross-sectional views showing forming of a thin film transistor portion, a gate line portion, and a data line portion of a liquid crystal panel using a four mask process according to the related art, respectively. In FIG. 2A, a gate electrode 60 is formed on a substrate 1, a gate insulating layer 62 is formed on the gate electrode 60, and a semiconductor layer 64 and source and drain electrodes 66 and 68 are sequentially formed on the gate insulating layer 62. The gate electrode 60, the semiconductor layer 64, and the source and drain electrodes 66 and 68 compose a thin film transistor (TFT) “T.” A passivation layer 72, which includes a drain contact hole 70, is formed on the TFT “T,” and a pixel electrode 74 is formed on the passivation layer 72. The drain contact hole 70 exposes the drain electrode 68 and the pixel electrode 74 is connected to the drain electrode 68 through the drain contact hole 70. The semiconductor layer 64 includes an active layer 64a of pure amorphous silicon (a-Si) and an ohmic contact layer 64b of impurity-doped amorphous silicon (n+ a-Si). The ohmic contact layer 64b between the source and drain electrodes 66 and 68 is eliminated, and the active layer 64a under the eliminated ohmic contact layer 64b is exposed to form a channel region “ch” of the TFT “T.” In a four mask process where the semiconductor layer 64 and the source and drain electrodes 66 and 68 are etched at one time, the channel region “ch” is formed by using a diffraction mask where light transmittance is adjusted by diffraction.
In FIG. 2B, a gate line 76, a gate insulating layer 62, and a passivation layer 72 are sequentially formed on a substrate 1, and the gate line 76 is simultaneously formed with formation of a gate electrode 60 (in FIG. 2A).
In FIG. 2C, a gate insulating layer 62 is formed on a substrate 1, and a semiconductor 64 and a data line 78 are sequentially formed on the gate insulating layer 62. The data line 78 is simultaneously formed with formation of the source and drain electrodes 66 and 68 (in FIG. 2A), and a passivation layer 72 is formed on the data line 78.
In general, since the steps of forming the semiconductor layer and the data line are performed at one time using a single photo mask in a four mask process, the semiconductor layer 64 has the same pattern as the data line 78 and the source and drain electrodes 66 and 68. Accordingly, a first accumulated thickness D1 (in FIG. 2B) of a gate line portion is different from a second accumulated thickness D2 (in FIG. 2C) of a data line portion. The difference between the first and second accumulated thicknesses “D1” and “D2” results from a difference between the thickness of the gate line 76 (in FIG. 2B) and the thickness of the semiconductor layer and the data line 64 and 78 (in FIG. 2C). For example, when the gate line has a thickness of 2700 Å, the gate insulating layer has a thickness of 4000 Å, the semiconductor layer has a thickness of 2000 Å, the data line has a thickness of 1500 Å, and the passivation layer has a thickness of 2000 Å. Accordingly, the first accumulated thickness D1 of the gate line portion is 8700 Å and the second accumulated thickness D2 of the data line portion is 9500 Å. The difference between the first and second accumulated thicknesses “D1” and “D2” is 800 Å. This difference creates a cell gap difference at a peripheral portion of the seal pattern, whereby non-uniformity of the cell gap creates spots in displayed images.